Will 100 Gigabit Create New Data Center Networking Startups? (Part 2)

In the earlier post on 100 Gigabit network, I discussed how the shift from designing in ASICs to FPGAs, while seemingly technical, is having major business implications for data center networkers. In this post, I look at the impact on FPGA developers.

As ASICs become more challenging economically, designers are increasingly turning to FPGAs to handle highspeed packet processing, which is an important development for Xilinx (XLNX) as the leading developer of FPGAs. By trading out the ASIC design cost, and replacing it with a royalty fee for an FPGA, circuit board and system designers are taking out a large capital expenditure and replacing it with an ongoing operating expense, which is the typical outsourcing economic equation. The increase in outsourcing is helping not just networkers, but their chip suppliers maintain some staying power, an important consideration for data centers managers concerned about suppliers' financial viability. Xilinx, for example, has been reporting strong gross margins, close to 65%, and the company has bounced around the 60s for most of the last decade. While this is lower than some other chip makers, including Mellanox (MLNX), Xilinx has made up for it by keeping R&D expenses to just 20% of revenue, compared to 30% of revenue at Mellanox. As a result, it has been able to post consistent net margins of around 20%. Rival Altera (ALTR) has posted similar margins, although its revenue remains about 20% lower than Xilinx’s. One factor behind Xilinx's lower gross margins is that inventory turns for the FPGA vendors are typically 5, which is not much higher than optical components suppliers. While other chip makers simply order wafers that ship to the fab suppliers with whom they have contracted, Xilinx and Altera must stock additional inventory for their distributors because their products require additional programmability before final use.

With FPGAs, Designers to Replace an Increasing Fixed Cost with an Ongoing Variable Cost
As ASICs become more challenging economically, designers are increasingly turning to FPGAs to handle highspeed packet processing, which is an important development for Xilinx (XLNX) as the leading developer of FPGAs. By trading out the ASIC design cost, and replacing it with a royalty fee for an FPGA, circuit board and system designers are taking out a large capital expenditure and replacing it with an ongoing operating expense, which is the typical outsourcing economic equation. The increase in outsourcing is helping not just networkers, but their chip suppliers maintain some staying power, an important consideration for data centers managers concerned about suppliers' financial viability. Xilinx, for example, has been reporting strong gross margins, close to 65%, and the company has bounced around the 60s for most of the last decade. While this is lower than some other chip makers, including Mellanox (MLNX), Xilinx has made up for it by keeping R&D expenses to just 20% of revenue, compared to 30% of revenue at Mellanox. As a result, it has been able to post consistent net margins of around 20%. Rival Altera (ALTR) has posted similar margins, although its revenue remains about 20% lower than Xilinx’s. One factor behind Xilinx's lower gross margins is that inventory turns for the FPGA vendors are typically 5, which is not much higher than optical components suppliers. While other chip makers simply order wafers that ship to the fab suppliers with whom they have contracted, Xilinx and Altera must stock additional inventory for their distributors because their products require additional programmability before final use.

Will 100 Gigabit Create New Data Center Networking Startups?

When MPLS (Multi-Protocol Label Switching) was released in the late 90s, Juniper (JNPR) entered the market with a proprietary packet forwarding ASIC, i.e. Application-Specific Integrated Circuit. When Gigabit Ethernet arrived around the same time, Extreme (EXTR) and Foundry (BRCD) introduced their proprietary packet forwarding ASICs. As 10 Gigabit Ethernet was being ratified in 2002, Force10 hit the scene with its proprietary packet forwarding ASIC. So who will develop a proprietary packet forwarding ASIC for 100 Gigabit? No one.

As process geometries in the semiconductor industry get smaller, the fixed design costs for each chip increase. Ten years ago, when 130 nanometer was still a state of the art technology, it cost around $10 million in R&D to develop an ASIC for forwarding packets. Today, at 40 nanometers, it costs well over $100 million.

Regardless of what happens with the economy, VCs fondness for the industry, or the development of the data center market, it is no longer financially possible for a startup equipment vendor to build a carrier-class forwarding architecture with its own ASIC, in addition to having to write an NMS, and sell a box. This is why startups like BLADE and Arista are focused on boxes that have LESS functionality than competing platforms from large vendors, but can also shoot frames across a network with less latency, as long as there aren't too many different places that traffic can go. In some respects, they're like the Model Ts of data networking, simple and inexpensive platforms with fewer configuration options but very strong price/performance.

In a follow up post, I'll look at what this means for programmable logic vendors like Xilinx (XLNX) and Altera (ALTR).