When MPLS (Multi-Protocol Label Switching) was released in the late 90s, Juniper (JNPR) entered the market with a proprietary packet forwarding ASIC, i.e. Application-Specific Integrated Circuit. When Gigabit Ethernet arrived around the same time, Extreme (EXTR) and Foundry (BRCD) introduced their proprietary packet forwarding ASICs. As 10 Gigabit Ethernet was being ratified in 2002, Force10 hit the scene with its proprietary packet forwarding ASIC. So who will develop a proprietary packet forwarding ASIC for 100 Gigabit? No one.
As process geometries in the semiconductor industry get smaller, the fixed design costs for each chip increase. Ten years ago, when 130 nanometer was still a state of the art technology, it cost around $10 million in R&D to develop an ASIC for forwarding packets. Today, at 40 nanometers, it costs well over $100 million.
Regardless of what happens with the economy, VCs fondness for the industry, or the development of the data center market, it is no longer financially possible for a startup equipment vendor to build a carrier-class forwarding architecture with its own ASIC, in addition to having to write an NMS, and sell a box. This is why startups like BLADE and Arista are focused on boxes that have LESS functionality than competing platforms from large vendors, but can also shoot frames across a network with less latency, as long as there aren't too many different places that traffic can go. In some respects, they're like the Model Ts of data networking, simple and inexpensive platforms with fewer configuration options but very strong price/performance.
In a follow up post, I'll look at what this means for programmable logic vendors like Xilinx (XLNX) and Altera (ALTR).